00001 /*This file has been prepared for Doxygen automatic documentation generation.*/ 00015 /* 00016 FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. 00017 00018 *************************************************************************** 00019 * * 00020 * If you are: * 00021 * * 00022 * + New to FreeRTOS, * 00023 * + Wanting to learn FreeRTOS or multitasking in general quickly * 00024 * + Looking for basic training, * 00025 * + Wanting to improve your FreeRTOS skills and productivity * 00026 * * 00027 * then take a look at the FreeRTOS eBook * 00028 * * 00029 * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * 00030 * http://www.FreeRTOS.org/Documentation * 00031 * * 00032 * A pdf reference manual is also available. Both are usually delivered * 00033 * to your inbox within 20 minutes to two hours when purchased between 8am * 00034 * and 8pm GMT (although please allow up to 24 hours in case of * 00035 * exceptional circumstances). Thank you for your support! * 00036 * * 00037 *************************************************************************** 00038 00039 This file is part of the FreeRTOS distribution. 00040 00041 FreeRTOS is free software; you can redistribute it and/or modify it under 00042 the terms of the GNU General Public License (version 2) as published by the 00043 Free Software Foundation AND MODIFIED BY the FreeRTOS exception. 00044 ***NOTE*** The exception to the GPL is included to allow you to distribute 00045 a combined work that includes FreeRTOS without being obliged to provide the 00046 source code for proprietary components outside of the FreeRTOS kernel. 00047 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT 00048 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 00049 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 00050 more details. You should have received a copy of the GNU General Public 00051 License and the FreeRTOS license exception along with FreeRTOS; if not it 00052 can be viewed here: http://www.freertos.org/a00114.html and also obtained 00053 by writing to Richard Barry, contact details for whom are available on the 00054 FreeRTOS WEB site. 00055 00056 1 tab == 4 spaces! 00057 00058 http://www.FreeRTOS.org - Documentation, latest information, license and 00059 contact details. 00060 00061 http://www.SafeRTOS.com - A version that is certified for use in safety 00062 critical systems. 00063 00064 http://www.OpenRTOS.com - Commercial support, development, porting, 00065 licensing and training services. 00066 */ 00067 00068 00069 00070 #ifndef PORTMACRO_H 00071 #define PORTMACRO_H 00072 00073 /*----------------------------------------------------------- 00074 * Port specific definitions. 00075 * 00076 * The settings in this file configure FreeRTOS correctly for the 00077 * given hardware and compiler. 00078 * 00079 * These settings should not be altered. 00080 *----------------------------------------------------------- 00081 */ 00082 #include <avr32/io.h> 00083 #include "intc.h" 00084 #include "compiler.h" 00085 00086 #ifdef __cplusplus 00087 extern "C" { 00088 #endif 00089 00090 00091 /* Type definitions. */ 00092 #define portCHAR char 00093 #define portFLOAT float 00094 #define portDOUBLE double 00095 #define portLONG long 00096 #define portSHORT short 00097 #define portSTACK_TYPE unsigned portLONG 00098 #define portBASE_TYPE portLONG 00099 00100 #define TASK_DELAY_MS(x) ( (x) /portTICK_RATE_MS ) 00101 #define TASK_DELAY_S(x) ( (x)*1000 /portTICK_RATE_MS ) 00102 #define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_RATE_MS ) 00103 00104 #define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL) 00105 00106 #if( configUSE_16_BIT_TICKS == 1 ) 00107 typedef unsigned portSHORT portTickType; 00108 #define portMAX_DELAY ( portTickType ) 0xffff 00109 #else 00110 typedef unsigned portLONG portTickType; 00111 #define portMAX_DELAY ( portTickType ) 0xffffffff 00112 #endif 00113 /*-----------------------------------------------------------*/ 00114 00115 /* Architecture specifics. */ 00116 #define portSTACK_GROWTH ( -1 ) 00117 #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) 00118 #define portBYTE_ALIGNMENT 4 00119 #define portNOP() {__asm__ __volatile__ ("nop");} 00120 /*-----------------------------------------------------------*/ 00121 00122 00123 /*-----------------------------------------------------------*/ 00124 00125 /* INTC-specific. */ 00126 #define DISABLE_ALL_EXCEPTIONS() Disable_global_exception() 00127 #define ENABLE_ALL_EXCEPTIONS() Enable_global_exception() 00128 00129 #define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt() 00130 #define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt() 00131 00132 #define DISABLE_INT_LEVEL(int_level) Disable_interrupt_level(int_level) 00133 #define ENABLE_INT_LEVEL(int_level) Enable_interrupt_level(int_level) 00134 00135 00136 /* 00137 * Debug trace. 00138 * Activated if and only if configDBG is nonzero. 00139 * Prints a formatted string to stdout. 00140 * The current source file name and line number are output with a colon before 00141 * the formatted string. 00142 * A carriage return and a linefeed are appended to the output. 00143 * stdout is redirected to the USART configured by configDBG_USART. 00144 * The parameters are the same as for the standard printf function. 00145 * There is no return value. 00146 * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc, 00147 * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock. 00148 */ 00149 #if configDBG 00150 #define portDBG_TRACE(...) \ 00151 { \ 00152 fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout); \ 00153 printf(__VA_ARGS__); \ 00154 fputs("\r\n", stdout); \ 00155 } 00156 #else 00157 #define portDBG_TRACE(...) 00158 #endif 00159 00160 00161 /* Critical section management. */ 00162 #define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS() 00163 #define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS() 00164 00165 00166 extern void vPortEnterCritical( void ); 00167 extern void vPortExitCritical( void ); 00168 00169 #define portENTER_CRITICAL() vPortEnterCritical(); 00170 #define portEXIT_CRITICAL() vPortExitCritical(); 00171 00172 00173 /* Added as there is no such function in FreeRTOS. */ 00174 extern void *pvPortRealloc( void *pv, size_t xSize ); 00175 /*-----------------------------------------------------------*/ 00176 00177 00178 /*=============================================================================================*/ 00179 00180 /* 00181 * Restore Context for cases other than INTi. 00182 */ 00183 #define portRESTORE_CONTEXT() \ 00184 { \ 00185 extern volatile unsigned portLONG ulCriticalNesting; \ 00186 extern volatile void *volatile pxCurrentTCB; \ 00187 \ 00188 __asm__ __volatile__ ( \ 00189 /* Set SP to point to new stack */ \ 00190 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)")\n\t" \ 00191 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)")\n\t" \ 00192 "ld.w r0, r8[0]\n\t" \ 00193 "ld.w sp, r0[0]\n\t" \ 00194 \ 00195 /* Restore ulCriticalNesting variable */ \ 00196 "ld.w r0, sp++\n\t" \ 00197 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)")\n\t" \ 00198 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)")\n\t" \ 00199 "st.w r8[0], r0\n\t" \ 00200 \ 00201 /* Restore R0..R7 */ \ 00202 "ldm sp++, r0-r7\n\t" \ 00203 /* R0-R7 should not be used below this line */ \ 00204 /* Skip PC and SR (will do it at the end) */ \ 00205 "sub sp, -2*4\n\t" \ 00206 /* Restore R8..R12 and LR */ \ 00207 "ldm sp++, r8-r12, lr\n\t" \ 00208 /* Restore SR */ \ 00209 "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */\ 00210 "mtsr "ASTRINGZ(AVR32_SR)", r0\n\t" \ 00211 /* Restore r0 */ \ 00212 "ld.w r0, sp[-9*4]\n\t" \ 00213 /* Restore PC */ \ 00214 "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \ 00215 ); \ 00216 \ 00217 /* Force import of global symbols from assembly */ \ 00218 ulCriticalNesting; \ 00219 pxCurrentTCB; \ 00220 } 00221 00222 00223 /* 00224 * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for AVR32_INTC_INT0..3 exceptions. 00225 * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception. 00226 * 00227 * Had to make different versions because registers saved on the system stack 00228 * are not the same between AVR32_INTC_INT0..3 exceptions and the scall exception. 00229 */ 00230 00231 // Task context stack layout: 00232 // R8 (*) 00233 // R9 (*) 00234 // R10 (*) 00235 // R11 (*) 00236 // R12 (*) 00237 // R14/LR (*) 00238 // R15/PC (*) 00239 // SR (*) 00240 // R0 00241 // R1 00242 // R2 00243 // R3 00244 // R4 00245 // R5 00246 // R6 00247 // R7 00248 // ulCriticalNesting 00249 // (*) automatically done for AVR32_INTC_INT0..AVR32_INTC_INT3, but not for SCALL 00250 00251 /* 00252 * The ISR used for the scheduler tick depends on whether the cooperative or 00253 * the preemptive scheduler is being used. 00254 */ 00255 #if configUSE_PREEMPTION == 0 00256 00257 /* 00258 * portSAVE_CONTEXT_OS_INT() for OS Tick exception. 00259 */ 00260 #define portSAVE_CONTEXT_OS_INT() \ 00261 { \ 00262 /* Save R0..R7 */ \ 00263 __asm__ __volatile__ ("stm --sp, r0-r7"); \ 00264 \ 00265 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ 00266 /* there is also no context save. */ \ 00267 } 00268 00269 /* 00270 * portRESTORE_CONTEXT_OS_INT() for Tick exception. 00271 */ 00272 #define portRESTORE_CONTEXT_OS_INT() \ 00273 { \ 00274 __asm__ __volatile__ ( \ 00275 /* Restore R0..R7 */ \ 00276 "ldm sp++, r0-r7\n\t" \ 00277 \ 00278 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ 00279 /* there is also no context restore. */ \ 00280 "rete" \ 00281 ); \ 00282 } 00283 00284 #else 00285 00286 /* 00287 * portSAVE_CONTEXT_OS_INT() for OS Tick exception. 00288 */ 00289 #define portSAVE_CONTEXT_OS_INT() \ 00290 { \ 00291 extern volatile unsigned portLONG ulCriticalNesting; \ 00292 extern volatile void *volatile pxCurrentTCB; \ 00293 \ 00294 /* When we come here */ \ 00295 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ 00296 \ 00297 __asm__ __volatile__ ( \ 00298 /* Save R0..R7 */ \ 00299 "stm --sp, r0-r7\n\t" \ 00300 \ 00301 /* Save ulCriticalNesting variable - R0 is overwritten */ \ 00302 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)")\n\t" \ 00303 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)")\n\t" \ 00304 "ld.w r0, r8[0]\n\t" \ 00305 "st.w --sp, r0\n\t" \ 00306 \ 00307 /* Check if AVR32_INTC_INT0 or higher were being handled (case where the OS tick interrupted another */ \ 00308 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ 00309 /* level and allow other lower interrupt level to occur). */ \ 00310 /* In this case we don't want to do a task switch because we don't know what the stack */ \ 00311 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ 00312 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ 00313 /* will just be restoring the interrupt handler, no way!!! */ \ 00314 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ 00315 "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */\ 00316 "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */\ 00317 "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */\ 00318 "brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)"\n\t" \ 00319 \ 00320 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ 00321 /* NOTE: we don't enter a critical section here because all interrupt handlers */ \ 00322 /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \ 00323 /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \ 00324 /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \ 00325 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)")\n\t" \ 00326 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)")\n\t" \ 00327 "ld.w r0, r8[0]\n\t" \ 00328 "st.w r0[0], sp\n" \ 00329 \ 00330 "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \ 00331 ); \ 00332 } 00333 00334 /* 00335 * portRESTORE_CONTEXT_OS_INT() for Tick exception. 00336 */ 00337 #define portRESTORE_CONTEXT_OS_INT() \ 00338 { \ 00339 extern volatile unsigned portLONG ulCriticalNesting; \ 00340 extern volatile void *volatile pxCurrentTCB; \ 00341 \ 00342 /* Check if AVR32_INTC_INT0 or higher were being handled (case where the OS tick interrupted another */ \ 00343 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ 00344 /* level and allow other lower interrupt level to occur). */ \ 00345 /* In this case we don't want to do a task switch because we don't know what the stack */ \ 00346 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ 00347 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ 00348 /* will just be restoring the interrupt handler, no way!!! */ \ 00349 __asm__ __volatile__ ( \ 00350 "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */\ 00351 "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */\ 00352 "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */\ 00353 "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__) \ 00354 ); \ 00355 \ 00356 /* Else */ \ 00357 /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \ 00358 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ 00359 portENTER_CRITICAL(); \ 00360 vTaskSwitchContext(); \ 00361 portEXIT_CRITICAL(); \ 00362 \ 00363 /* Restore all registers */ \ 00364 \ 00365 __asm__ __volatile__ ( \ 00366 /* Set SP to point to new stack */ \ 00367 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)")\n\t" \ 00368 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)")\n\t" \ 00369 "ld.w r0, r8[0]\n\t" \ 00370 "ld.w sp, r0[0]\n" \ 00371 \ 00372 "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":\n\t" \ 00373 \ 00374 /* Restore ulCriticalNesting variable */ \ 00375 "ld.w r0, sp++\n\t" \ 00376 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)")\n\t" \ 00377 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)")\n\t" \ 00378 "st.w r8[0], r0\n\t" \ 00379 \ 00380 /* Restore R0..R7 */ \ 00381 "ldm sp++, r0-r7\n\t" \ 00382 \ 00383 /* Now, the stack should be R8..R12, LR, PC and SR */ \ 00384 "rete" \ 00385 ); \ 00386 \ 00387 /* Force import of global symbols from assembly */ \ 00388 ulCriticalNesting; \ 00389 pxCurrentTCB; \ 00390 } 00391 00392 #endif 00393 00394 00395 /* 00396 * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception. 00397 * 00398 * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode. 00399 * 00400 */ 00401 #define portSAVE_CONTEXT_SCALL() \ 00402 { \ 00403 extern volatile unsigned portLONG ulCriticalNesting; \ 00404 extern volatile void *volatile pxCurrentTCB; \ 00405 \ 00406 /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \ 00407 /* If SR[M2:M0] == 001 */ \ 00408 /* PC and SR are on the stack. */ \ 00409 /* Else (other modes) */ \ 00410 /* Nothing on the stack. */ \ 00411 \ 00412 /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \ 00413 /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \ 00414 /* in an interrupt|exception handler. */ \ 00415 \ 00416 __asm__ __volatile__ ( \ 00417 /* in order to save R0-R7 */ \ 00418 "sub sp, 6*4\n\t" \ 00419 /* Save R0..R7 */ \ 00420 "stm --sp, r0-r7\n\t" \ 00421 \ 00422 /* in order to save R8-R12 and LR */ \ 00423 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ 00424 "sub r7, sp,-16*4\n\t" \ 00425 /* Copy PC and SR in other places in the stack. */ \ 00426 "ld.w r0, r7[-2*4]\n\t" /* Read SR */\ 00427 "st.w r7[-8*4], r0\n\t" /* Copy SR */\ 00428 "ld.w r0, r7[-1*4]\n\t" /* Read PC */\ 00429 "st.w r7[-7*4], r0\n\t" /* Copy PC */\ 00430 \ 00431 /* Save R8..R12 and LR on the stack. */ \ 00432 "stm --r7, r8-r12, lr\n\t" \ 00433 \ 00434 /* Arriving here we have the following stack organizations: */ \ 00435 /* R8..R12, LR, PC, SR, R0..R7. */ \ 00436 \ 00437 /* Now we can finalize the save. */ \ 00438 \ 00439 /* Save ulCriticalNesting variable - R0 is overwritten */ \ 00440 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)")\n\t" \ 00441 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)")\n\t" \ 00442 "ld.w r0, r8[0]\n\t" \ 00443 "st.w --sp, r0" \ 00444 ); \ 00445 \ 00446 /* Disable the its which may cause a context switch (i.e. cause a change of */ \ 00447 /* pxCurrentTCB). */ \ 00448 /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \ 00449 /* critical section because it is a global structure. */ \ 00450 portENTER_CRITICAL(); \ 00451 \ 00452 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ 00453 __asm__ __volatile__ ( \ 00454 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)")\n\t" \ 00455 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)")\n\t" \ 00456 "ld.w r0, r8[0]\n\t" \ 00457 "st.w r0[0], sp" \ 00458 ); \ 00459 } 00460 00461 /* 00462 * portRESTORE_CONTEXT() for SupervisorCALL exception. 00463 */ 00464 #define portRESTORE_CONTEXT_SCALL() \ 00465 { \ 00466 extern volatile unsigned portLONG ulCriticalNesting; \ 00467 extern volatile void *volatile pxCurrentTCB; \ 00468 \ 00469 /* Restore all registers */ \ 00470 \ 00471 /* Set SP to point to new stack */ \ 00472 __asm__ __volatile__ ( \ 00473 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)")\n\t" \ 00474 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)")\n\t" \ 00475 "ld.w r0, r8[0]\n\t" \ 00476 "ld.w sp, r0[0]" \ 00477 ); \ 00478 \ 00479 /* Leave pxCurrentTCB variable access critical section */ \ 00480 portEXIT_CRITICAL(); \ 00481 \ 00482 __asm__ __volatile__ ( \ 00483 /* Restore ulCriticalNesting variable */ \ 00484 "ld.w r0, sp++\n\t" \ 00485 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)")\n\t" \ 00486 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)")\n\t" \ 00487 "st.w r8[0], r0\n\t" \ 00488 \ 00489 /* skip PC and SR */ \ 00490 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ 00491 "sub r7, sp, -10*4\n\t" \ 00492 /* Restore r8-r12 and LR */ \ 00493 "ldm r7++, r8-r12, lr\n\t" \ 00494 \ 00495 /* RETS will take care of the extra PC and SR restore. */ \ 00496 /* So, we have to prepare the stack for this. */ \ 00497 "ld.w r0, r7[-8*4]\n\t" /* Read SR */\ 00498 "st.w r7[-2*4], r0\n\t" /* Copy SR */\ 00499 "ld.w r0, r7[-7*4]\n\t" /* Read PC */\ 00500 "st.w r7[-1*4], r0\n\t" /* Copy PC */\ 00501 \ 00502 /* Restore R0..R7 */ \ 00503 "ldm sp++, r0-r7\n\t" \ 00504 \ 00505 "sub sp, -6*4\n\t" \ 00506 \ 00507 "rets" \ 00508 ); \ 00509 \ 00510 /* Force import of global symbols from assembly */ \ 00511 ulCriticalNesting; \ 00512 pxCurrentTCB; \ 00513 } 00514 00515 00516 /* 00517 * The ISR used depends on whether the cooperative or 00518 * the preemptive scheduler is being used. 00519 */ 00520 #if configUSE_PREEMPTION == 0 00521 00522 /* 00523 * ISR entry and exit macros. These are only required if a task switch 00524 * is required from the ISR. 00525 */ 00526 #define portENTER_SWITCHING_ISR() \ 00527 { \ 00528 /* Save R0..R7 */ \ 00529 __asm__ __volatile__ ("stm --sp, r0-r7"); \ 00530 \ 00531 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ 00532 /* there is also no context save. */ \ 00533 } 00534 00535 /* 00536 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 00537 */ 00538 #define portEXIT_SWITCHING_ISR() \ 00539 { \ 00540 __asm__ __volatile__ ( \ 00541 /* Restore R0..R7 */ \ 00542 "ldm sp++, r0-r7\n\t" \ 00543 \ 00544 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ 00545 /* there is also no context restore. */ \ 00546 "rete" \ 00547 ); \ 00548 } 00549 00550 #else 00551 00552 /* 00553 * ISR entry and exit macros. These are only required if a task switch 00554 * is required from the ISR. 00555 */ 00556 #define portENTER_SWITCHING_ISR() \ 00557 { \ 00558 extern volatile unsigned portLONG ulCriticalNesting; \ 00559 extern volatile void *volatile pxCurrentTCB; \ 00560 \ 00561 /* When we come here */ \ 00562 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ 00563 \ 00564 __asm__ __volatile__ ( \ 00565 /* Save R0..R7 */ \ 00566 "stm --sp, r0-r7\n\t" \ 00567 \ 00568 /* Save ulCriticalNesting variable - R0 is overwritten */ \ 00569 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)")\n\t" \ 00570 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)")\n\t" \ 00571 "ld.w r0, r8[0]\n\t" \ 00572 "st.w --sp, r0\n\t" \ 00573 \ 00574 /* Check if AVR32_INTC_INT0 or higher were being handled (case where the OS tick interrupted another */ \ 00575 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ 00576 /* level and allow other lower interrupt level to occur). */ \ 00577 /* In this case we don't want to do a task switch because we don't know what the stack */ \ 00578 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ 00579 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ 00580 /* will just be restoring the interrupt handler, no way!!! */ \ 00581 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ 00582 "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */\ 00583 "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */\ 00584 "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */\ 00585 "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)"\n\t" \ 00586 \ 00587 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ 00588 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)")\n\t" \ 00589 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)")\n\t" \ 00590 "ld.w r0, r8[0]\n\t" \ 00591 "st.w r0[0], sp\n" \ 00592 \ 00593 "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \ 00594 ); \ 00595 } 00596 00597 00598 /* 00599 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 00600 */ 00601 #define portEXIT_SWITCHING_ISR() \ 00602 { \ 00603 extern volatile unsigned portLONG ulCriticalNesting; \ 00604 extern volatile void *volatile pxCurrentTCB; \ 00605 \ 00606 __asm__ __volatile__ ( \ 00607 /* Check if AVR32_INTC_INT0 or higher were being handled (case where the OS tick interrupted another */ \ 00608 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ 00609 /* level and allow other lower interrupt level to occur). */ \ 00610 /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \ 00611 /* did not previously save SP in its TCB. */ \ 00612 "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */\ 00613 "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */\ 00614 "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */\ 00615 "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)"\n\t" \ 00616 \ 00617 /* If a switch is required then we just need to call */ \ 00618 /* vTaskSwitchContext() as the context has already been */ \ 00619 /* saved. */ \ 00620 "cp.w r12, 1\n\t" /* Check if Switch context is required. */\ 00621 "brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C" \ 00622 ); \ 00623 \ 00624 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ 00625 portENTER_CRITICAL(); \ 00626 vTaskSwitchContext(); \ 00627 portEXIT_CRITICAL(); \ 00628 \ 00629 __asm__ __volatile__ ( \ 00630 "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":\n\t" \ 00631 /* Restore the context of which ever task is now the highest */ \ 00632 /* priority that is ready to run. */ \ 00633 \ 00634 /* Restore all registers */ \ 00635 \ 00636 /* Set SP to point to new stack */ \ 00637 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)")\n\t" \ 00638 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)")\n\t" \ 00639 "ld.w r0, r8[0]\n\t" \ 00640 "ld.w sp, r0[0]\n" \ 00641 \ 00642 "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":\n\t" \ 00643 \ 00644 /* Restore ulCriticalNesting variable */ \ 00645 "ld.w r0, sp++\n\t" \ 00646 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)")\n\t" \ 00647 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)")\n\t" \ 00648 "st.w r8[0], r0\n\t" \ 00649 \ 00650 /* Restore R0..R7 */ \ 00651 "ldm sp++, r0-r7\n\t" \ 00652 \ 00653 /* Now, the stack should be R8..R12, LR, PC and SR */ \ 00654 "rete" \ 00655 ); \ 00656 \ 00657 /* Force import of global symbols from assembly */ \ 00658 ulCriticalNesting; \ 00659 pxCurrentTCB; \ 00660 } 00661 00662 #endif 00663 00664 00665 #define portYIELD() {__asm__ __volatile__ ("scall");} 00666 00667 /* Task function macros as described on the FreeRTOS.org WEB site. */ 00668 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) 00669 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) 00670 00671 #define inline 00672 00673 #ifdef __cplusplus 00674 } 00675 #endif 00676 00677 #endif /* PORTMACRO_H */